This disclosure relates generally to the field of phase-locked loops, and more particularly to a stacked CMOS phase-locked loop.
A phase-locked loop (PLL) is a system that generates an output signal whose phase is related to the phase of an input signal. PLLs include a phase frequency detector (PFD), a charge pump, a low-pass filter, a voltage controlled oscillator (VCO), and a feedback path from the VCO to the phase frequency detector. Phase-locked loops typically include divider circuits, which divide the input signal and the feedback signal to the phase frequency detector.
The phase frequency detector and the low-pass filter are analog circuits, while the VCO and the dividers are high speed circuits. The VCO and dividers typically produce large amounts of interference and noise on power and signal lines, and through substrate coupling, in the PLL. The analog circuits tend to be very sensitive to noise.
The frequency response of the VCO with respect to frequency is known as KVCO. KVCO is determined by the size of the capacitors in the low-pass filter, wherein larger capacitors result in larger KVCOs. There are advantages and disadvantages associated with a large KVCO. The advantages include larger VCO frequency range and higher tolerance to supply voltage and temperature variations. The disadvantages include the need for larger chip die sizes to accommodate the larger capacitors, and greater VCO noise. The disadvantages tend to outweigh the advantages.